Calculation of Mean Shift for a Binary Multiplier Using 2, 3, or 4 Bits at a Time

1 December 1967

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electronic Computers

Vol. EC-16 (6) , 864-866
https://doi.org/10.1109/pgec.1967.264752

Abstract

Binary multiplication can be speeded up by taking two or more bits of the multiplier at a time. This note describes an exact method, based on the use of a discrete-time, finite-state system model, for calculating the gain in multiplication speed resulting from such a scheme. It is shown that the gain in speed is less than what had previously been obtained using an approximation formula.

Keywords

PATTERN RECOGNITION
INFORMATION THEORY
MACHINE LEARNING
CHARACTER RECOGNITION
ADAPTIVE SIGNAL DETECTION
DECISION MAKING
ALGORITHM DESIGN AND ANALYSIS
PROBABILITY

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