A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic
- 22 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- Floating body effects in partially-depleted SOI CMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 0.5 V SIMOX-MTCMOS circuit with 200 ps logic gatePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- 0.5 V SOI CMOS pass-gate logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- History dependence of non-fully depleted (NFD) digital SOI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 500 MHz 1-stage 32 bit ALU with self-running test circuitPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- High-Speed SOI 1/8 Frequency Divider Using Field-Shield Body-Fixed StructureJapanese Journal of Applied Physics, 1996
- A room temperature 0.1 μm CMOS on SOIIEEE Transactions on Electron Devices, 1994
- A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logicIEEE Journal of Solid-State Circuits, 1990