Enhancing CMOS Transistor Performance Using Lattice-Mismatched Materials in Source/Drain Regions

1 January 2006

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 1-2
https://doi.org/10.1109/istdm.2006.246557

Abstract

Strain engineering using lattice-mismatched S/D in transistors and their combination with other stressors and optimum surface/channel orientations is very attractive and important for the continued improvement of CMOS performance in addition to device scaling

Keywords

SILICON CARBIDE
SILICON COMPOUNDS
CAPACITIVE SENSORS
SILICON GERMANIUM
GERMANIUM SILICON ALLOYS
MOSFETS
SEMICONDUCTOR MATERIALS
TENSILE STRESS
LATTICES
COMPRESSIVE STRESS

This publication has 1 reference indexed in Scilit:

Strained Channel Transistor Using Strain Field Induced By Source and Drain Stressors
MRS Proceedings, 2004