Ion implantation of neon in silicon for planar amorphous isolation

20 July 1978

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 14 (15) , 460-462
https://doi.org/10.1049/el:19780310

Abstract

A new planar isolation technique for silicon integrated circuits is presented. The process uses neon implantation to create high-resistivity regions of amorphous silicon between active devices on a common substrate. Excellent surface planarity is obtained, and no high-temperature processing ii required. Results on test devices and an amorphous isolated m.n.o.s. capacitor memory are described.

Keywords

INTEGRATED CIRCUITS
MNOS CAPACITOR MEMORY
PLANAR ISOLATION TECHNIQUE
SURFACE PLANARITY
MONOLITHIC INTEGRATED CIRCUITS
NE ION IMPLANTATION
PLANAR AMORPHOUS ISOLATION

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