Endurance of EEPROMs with On-Chip Error Correction
- 1 June 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Reliability
- Vol. R-36 (2) , 222-223
- https://doi.org/10.1109/TR.1987.5222346
Abstract
This paper presents an endurance model for EEPROMs utilizing an on-chip error-correction code (ECC). This is necessary to determine the effect that ECC schemes have upon endurance (and therefore, reliability) of EEPROMs. EEPROM technology is briefly discussed.Keywords
This publication has 1 reference indexed in Scilit:
- Evaluating MTBF Approximations for Simple Maintained SystemsIEEE Transactions on Reliability, 1986