A new CMOS isolation technique has been developed for reducing isolation width to a 1/4 µm with large latchup immunity. This technique is supported by three key processes. The first is to form 1/4 µm thick insulator films on trench sidewalls, which are shaped perpendicularly to the substrate surface plane. The second is to refill the trenches with selectively grown single-crystal silicon with a planar surface. The third is to form a low-resistance well for latchup prevention. The CMOS devices are composed of n-channel devices fabricated on a p-type substrate and p-channel devices fabricated on an n-type epi-layer. In this isolation structure, a parasitic MIS operation with vertical channel induces large leakage currents along the isolation sidewalls. However, the highly doped p-type region, due to deep boron implant in the p-type substrate, is effective to suppress parasitic operation. Submicrometer-gate CMOS inverter operation is shown, when the channel stop implant is carried out.