VLSI and WSI associative string processors for structured data processing
- 1 January 1986
- journal article
- Published by Institution of Engineering and Technology (IET) in IEE Proceedings E Computers and Digital Techniques
- Vol. 133 (3) , 153-162
- https://doi.org/10.1049/ip-e.1986.0020
Abstract
A novel fine-grain parallel-processing microelectronic architecture is proposed as a cost-effective building-block for fifth-generation computer systems. Based on a fully programmable associative string processing computational structure, the architecture provides particularly flexible support and manipulation of abstract data structures over a wide range of information processing tasks. Moreover, the architecture is well suited to the technological constraints of VLSI chip and, especially, WSI device fabrication. The paper describes the ASP (associative string processor) architecture and its instruction set. The style of associative string processing is introduced with three algorithms, illustrating both relational and arithmetic operations. Current projects leading to VLSI ASP chips and WSI ASP devices are discussed and ‘ball-park’ performance figures are given.Keywords
This publication has 3 references indexed in Scilit:
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- Introduction to Associative ProcessorsPublished by Springer Nature ,1977
- Associative Processing of Non-Numerical InformationPublished by Springer Nature ,1977