A 65 MHz 16-tap FIR filter chip with on-chip video delay lines
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 3050-3052 vol.4
- https://doi.org/10.1109/iscas.1990.112655
Abstract
The VLSI design of a 16-tap finite impulse response (FIR) filter chip with programmable line delays for video applications is described. The chip is fabricated in 0.9- mu m CMOS technology. It is tested at sample rates up to 65 MHz. The chip contains about 600000 devices in less than 22 mm/sup 2/ of silicon area.Keywords
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