Smart-pixel cellular neural networks in analog current-mode CMOS technology
- 1 January 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 29 (8) , 895-905
- https://doi.org/10.1109/4.297693
Abstract
This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOSBJTs connected in a Darlington structure. Pixel smartness is achieved by exploiting the Cellular Neural Network paradigm [1], [2], incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation,technique and give measurements,from two 16 × 16 prototypes in a single-poly double-metal CMOS n-well 1.6μm technology. In addition to the sensory and processing circuitry, both chips incorporate lightadaptationcircuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm ,, with a power consumption down to 105 μW/unit and image processing timesKeywords
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