Extended AC Conductance–Bias Method Considering Semiconductor Conductance and Capacitance in MOS Structure

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Abstract
The influence of the semiconductor conductance G s and the interface trap conductance G p on MOS ac conductance is revealed in all bias regions from inversion to accumulation in the high frequency range, for example, 1 kHz-1 MHz. The conductance–bias (G-V) method is extended considerably in order to clarify the interface state characteristics more easily. Under the bias conditions of accumulation and weak inversion, the measured results are successfully explained by the newly-introduced semiconductor conductance G s. The conductance curve of the interface and oxide traps with respect to the semiconductor capacitance C s shows a peak in the depletion region. The semiconductor conductance curve with respect to C s is linear in the accumulation region.