Hierarchical algorithm for a partition problem using simulated annealing: application to placement in VLSI layout

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Abstract
A hierarchical simulated annealing (HSA) method for a partition problem is proposed for a realization of parallelization to reduce computational time. The HSA method hierarchically divides a given problem into some sub-problems applying the SA method at each stage and makes it possible automatically to choose suitable parameters in the cost functions at each stage of the hierarchical computation. Theoretical consideration and application of the HSA method to the placement problem in VLSI layout show that the HSA method can accomplish much more reduction of computational time and a better final result than the original SA method.

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