A Computer-Oriented Factoring Algorithm for NOR Logic Design

1 December 1965

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electronic Computers

Vol. EC-14 (6) , 868-874
https://doi.org/10.1109/pgec.1965.264081

Abstract

Because transistor NOR gates allow only a liitmed number of inputs, NOR equations must be factored before they can be implemented. An easily programmed algorithm is developed which rapidly generates a subset of factors, selects optimum factors, and indicates a realization for the factored equation based on the relation A ↓ B ↓ C ↓ D = [(A ↓ B) ↓] ↓ C ↓ D. A method for preventing excessive fan-out is also presented.

Keywords

LOGIC DESIGN
EQUATIONS
CIRCUIT SYNTHESIS
ALGORITHM DESIGN AND ANALYSIS
COST FUNCTION
LOGIC CIRCUITS
PACKAGING
HARDWARE
TELLURIUM
POWER GENERATION

This publication has 1 reference indexed in Scilit:

Synthesizing Minimal Stroke and Dagger Functions
IRE Transactions on Circuit Theory, 1960