Design verification and reachability analysis using algebraic manipulation
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Compositional model checkingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Implicit state enumeration of finite state machines using BDD'sPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Sequential circuit verification using symbolic model checkingPublished by Association for Computing Machinery (ACM) ,1990
- Verification of interacting sequential circuitsPublished by Association for Computing Machinery (ACM) ,1990
- An algorithmic procedure for checking safety properties of protocolsIEEE Transactions on Communications, 1989
- Research on Automatic Verification of Finite-State Concurrent SystemsAnnual Review of Computer Science, 1987
- Communicating sequential processesCommunications of the ACM, 1978