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Gross delay defect evaluation for a CMOS logic design system product
Home
Publications
Gross delay defect evaluation for a CMOS logic design system product
Gross delay defect evaluation for a CMOS logic design system product
OB
O. Bula
O. Bula
JM
J. Moser
J. Moser
JT
J. Trinko
J. Trinko
MW
M. Weissman
M. Weissman
FW
F. Woytowich
F. Woytowich
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1 March 1990
journal article
Published by
IBM
in
IBM Journal of Research and Development
Vol. 34
(2)
,
325-338
https://doi.org/10.1147/rd.342.0325
Abstract
No abstract available
Cited
Cited by 18 articles
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