Suppressing Flash EEPROM Erase Leakage With Negative Gate Bias And LDD Erase Junction

Publisher Website

1 January 1993

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 81-82
https://doi.org/10.1109/vlsit.1993.760255

Abstract

No abstract available

This publication has 1 reference indexed in Scilit:

Drain-avalanche and hole-trapping induced gate leakage in thin-oxide MOS devices
IEEE Electron Device Letters, 1988