SOI‐bipolar transistors were fabricated by Si epitaxial layers on epitaxial layers grown on Si wafers. Leakage current increased due to crystalline defects on the Si layer. By using solid‐phase epitaxy (SPE) or seedless zone melting recrystallization (ZMR), crystalline defects were reduced. Stacking faults were reduced from 108/cm2 to less than 102/cm2 by solid‐phase epitaxial growth of the amorphous Si layer. The leakage current of a bipolar transistor fabricated on a defect‐reduced Si layer was less than 1 nA at 10 V. Both stacking faults and dislocations were reduced by ZMR of the Si layer epitaxially grown on . Dielectrically isolated bipolar transistors with low‐leakage current were obtained.