Statistical Techniques of Timing Verification
- 1 January 1983
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 0738100X,p. 396-402
- https://doi.org/10.1109/dac.1983.1585683
Abstract
Timing verification of VLSI designs using statistical techniques such as those implemented in Hitchcock's Timing Analysis [1] permit a far more precise assessment of machine performance than previous techniques. The accuracy of these results is affected by proper user specification of statistical techniques in order to insure a properly verified design. This paper both outlines the mathematical derivations and illustrates the magnitude of the improvements to be obtained.Keywords
This publication has 3 references indexed in Scilit:
- Timing Verification and the Timing Analysis programPublished by Association for Computing Machinery (ACM) ,1982
- Verification of timing constraints on large digital systemsPublished by Association for Computing Machinery (ACM) ,1980
- Pert as an Aid to Logic DesignIBM Journal of Research and Development, 1966