An adaptive equalizing maximum likelihood decoding LSI for magnetic recording systems

1 January 1993

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 220-221
https://doi.org/10.1109/isscc.1993.280040

Abstract

Describes a fully digital microprogrammable signal processor chip for magnetic tape (MT) recording systems which contains an adaptive equalizer, a maximum-likelihood decoder for various codes, a clock-recovery circuit, and an analog-phase-locked loop (PLL). Microprogrammable signal-processing cores reduce the number of gates by 40% compared to conventional design and provide flexibility for various recording codes. The micrograph of the fabricated LSI is shown. The process is in 1.0- mu m CMOS. Performance is summarized, and the analog input and equalized wave forms are presented.<>

Keywords

ADAPTIVE EQUALIZERS
MAXIMUM LIKELIHOOD DECODING
LARGE SCALE INTEGRATION
SIGNAL PROCESSING
DIGITAL MAGNETIC RECORDING
CLOCKS
MAGNETIC CIRCUITS
PHASE LOCKED LOOPS
MAGNETIC CORES
SIGNAL DESIGN

This publication has 1 reference indexed in Scilit:

Sequence (Viterbi-equivalent) decoding
IEEE Transactions on Magnetics, 1988