VLSI Implementation of Digital Fourier Transforms.
- 1 November 1982
- report
- Published by Defense Technical Information Center (DTIC)
Abstract
The construction of Fast Fourier Transform (FFT) processors is discussed. Pipeline and parallel-pipeline organizations are developed and are shown to meet the constraints imposed by VLSI. Various circuit technologies for the construction of these processors are compared, and the description of a set of NMOS chips are given. A technique for reducing the latency of the adders internal to the chips is also presented. Finally, a broad set of possible FFT organizations is discussed. (Author)Keywords
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