CMOS/SOS NAND Gate Sapphire Photocurrent Compensation

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Abstract
Sapphire photocurrent is the dominant transient radiation response of CMOS/SOS circuits at high dose rates. Radiation-induced leakage current flowing through this photoresistive path accounts for most of the SOS transistor drain photocurrent observed experimentally. Sapphire photoconduction effects were modeled by incorporating radiation-induced linear photoconductance models in parallel with the channel conductances of the MOS transistors. This approach was used to predict the performance of CMOS/SOS NAND gates at high dose rates. NAND gates designed in accordance with optimum-W geometry rules for sapphire photocurrent compensation are predicted to have symmetrical dose-rate failure thresholds exceeding 1010 rads/sec. Radiation test results from experimental CMOS/SOS NAND gates have demonstrated dose-rate failure thresholds in the range from 2 × 1010 to 1011 rads/sec. The maximum achievable dose-rate failure threshold is approximately inversely proportional to fan-in. Consequently, more-radiation-resistant CMOS/SOS digital integrated circuits can be designed using CMOS/SOS NAND gates having limited fan-in. This design guide is practical, since it presents no serious problem with respect to either die size or circuit complexity.

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