A 64-ch Time Memory Cell module with a DSP and a VME interface
- 1 August 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 41 (4) , 1187-1191
- https://doi.org/10.1109/23.322881
Abstract
No abstract availableThis publication has 2 references indexed in Scilit:
- Development of a CMOS time memory cell VLSI and a CAMAC module with 0.5 ns resolutionIEEE Transactions on Nuclear Science, 1992
- A CMOS four-channel*1K time memory LSI with 1-ns/b resolutionIEEE Journal of Solid-State Circuits, 1992