Algorithm design for a 30-bit integrated logarithmic processor

Abstract
A description is given of the architecture of an integrated processor that is capable of performing addition and subtraction of 30-b numbers with 20 fractional bits in the logarithmic number system. Previous techniques would require 70 Mb of ROM to implement this processor, which is not feasible for a single-chip implementation. The techniques presented here use a factor of 275 less memory. The key to this is the use of a linear approximation of the nonlinear functions stored in the lookup tables. The functions involved are highly nonlinear in some regions, so variable size regions are used for the approximation. The use of linear approximation alone would still require over 565 kb of ROM. Further compression is obtained by using linear approximation with differential coding of each table. The compression is chosen to minimize ROM size and obtains a further reduction of 55%. A total of 260 kb of ROM is required to implement the processor.

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