Power Minimization Problems of Logic Networks
- 1 February 1974
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-23 (2) , 153-165
- https://doi.org/10.1109/T-C.1974.223878
Abstract
As a method for greatly reducing power dissipation in logic networks, we propose some logic organization techniques for logic networks. By such techniques, their power dissipation is to be minimized under certain input conditions, or the average power dissipation in the whole network should be minimized. A logic network in which these problems are taken into account will be called a power minimized logic circuit (PML).Keywords
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