Multilevel synthesis minimizing the routing factor
- 4 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- A channelless layout for multilevel synthesis with compiled cellsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- ASYL: A Rule-Based System for Controller SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987