Implementing Neon: a 256-bit graphics accelerator
- 1 January 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 19 (2) , 58-69
- https://doi.org/10.1109/40.755468
Abstract
High-performance 3D graphics accelerators traditionally require multiple chips on multiple boards. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL 3D rendering, and X11 and Windows/NT 2D rendering. Since our pin budget limited memory bandwidth, we designed Neon from the memory system upward to reduce bandwidth requirements. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital's Alpha CPUs. Neon-based boards compete well against other workstation accelerators, but cost much less due to a small part count and use of commodity SDRAMs.Keywords
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