Leveraging the Multiprocessing Capabilities of Modern Network Processors for Cryptographic Acceleration

1 January 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 235-238
https://doi.org/10.1109/nca.2005.28

Abstract

The Kasumi block cipher provides integrity and confidentiality services for 3G wireless networks, but it also forms a bottleneck due to its computational overhead. Especially in infrastructure equipment with data streams from multiple connections entering and leaving the network processor the critical performance issue needs to be addressed. In this paper we present a highly scalable bit sliced implementation of the Kasumi block cipher for the Intel IXP 28xx family of network processors. It can achieve a maximum theoretical encryption rate of up to 2 Gb/s when run in parallel on all 16 on-chip microengines

Keywords

CRYPTOGRAPHY
ACCELERATION
RANDOM ACCESS MEMORY
REGISTERS
DATA SECURITY
COMPUTER ARCHITECTURE
COMPUTER NETWORKS
ENGINES
READ-WRITE MEMORY
CLOCKS

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