A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
- 23 February 2003
- proceedings article
- Published by Association for Computing Machinery (ACM)
- p. 207-215
- https://doi.org/10.1145/611817.611848
Abstract
A fully pipelined implementation of the Advanced Encryption Standard encryption algorithm with 128-bit input and key length (AES-128) was implemented on Xilinx' Virtex-E and Virtex-II devices. The design is called SIG-AES-E and it implements the S-boxes combinatorially and thus requires no internal memory. It is concluded, that SIG-AES-E is faster than other published FPGA-based implementations of the AES-128 encryption algorithm.Keywords
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