Bare die test

Abstract

The author describes a bare die test approach that uses a temporary interconnect technique overlaid on a reconstructed pseudo-wafer of individual bare dice. This overlay technique maps design-specific pad locations to a standard grid that can be tested with a universal membrane probe. The proposed approach allows the development cost of a thin-film membrane probe to be shared across many die types, thus reducing the cost and complexity of tooling new die types. An experiment performed to validate this approach is described.

Keywords

PROBES
BIOMEMBRANES
WAFER SCALE INTEGRATION
COSTS
LABORATORIES
CIRCUIT TESTING
INTEGRATED CIRCUIT PACKAGING
FOUNDRIES
INTEGRATED CIRCUIT INTERCONNECTIONS
THIN FILM CIRCUITS

This publication has 1 reference indexed in Scilit:

Wafer-level testing with a membrane probe
IEEE Design & Test of Computers, 1989