A 150-mhz 4-bank 64m-bit Sdram With Address Incrementing Pipeline Scheme
- 24 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- 3-dimensional stacked capacitor cell for 16 M and 64 M DRAMSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- 250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- 16 Mbit synchronous DRAM with 125 Mbyte/sec data ratePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993