Reconfiguring processor arrays using multiple-track models: the 3-track-1-spare-approach

1 January 1993

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. 42 (11) , 1281-1293
https://doi.org/10.1109/12.247834

Abstract

Present new results on systematic procedures for reconfiguring processor arrays in the presence of faulty processors. In particular, the authors consider models that use multiple tracks along every channel and a single spare row (or column) of processing elements (PEs) along each boundary of the array. In the presence of faulty PEs the general methodology for reconfiguration involves replacing ever

Keywords

FAULT TOLERANT COMPUTING
MULTIPROCESSING SYSTEMS
RECONFIGURABLE ARCHITECTURES
REDUNDANCY
3-TRACK-1-SPARE-APPROACH
COMPENSATION PATHS
CONTINUITY
FAULT-TOLERANT ARCHITECTURE
FAULTY PE
FAULTY PROCESSORS
LOGICAL SUBSTITUTIONS
MULTI-TRACK-MODELS
MULTIPLE-TRACK MODELS
NONINTERSECTION
POLYNOMIAL-TIME RECONFIGURATION ALGORITHMS
PROCESSOR ARRAYS
RECONFIGURATION PROBABILITY
RECONFIGURING
ROUTING CHANNELS

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