Graph-Optimization Techniques for IC Layout and Compaction

1 January 1983

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 0738100X,p. 113-120
https://doi.org/10.1109/dac.1983.1585635

Abstract

This paper describes a new approach for IC layout and compaction. The compaction problem is translated into a mixed integer-linear programming problem of a very special form. A graph based optimization algorithm is used to solve the resulting problem. An experimental program that uses the above techniques is described. The program could be used either as an aid to hand layout or as the bottom part of an automatic layout generation program.

Keywords

INTEGRATED CIRCUIT LAYOUT
COMPACTION
LIBRARIES
SHAPE
COMPUTER SCIENCE
APPLICATION SPECIFIC INTEGRATED CIRCUITS
LOGIC DESIGN
LOGIC CIRCUITS
DIGITAL CIRCUITS
MINIMIZATION

This publication has 2 references indexed in Scilit:

SLIP: symbolic layout of integrated circuits with compaction
Computer-Aided Design, 1978
A sequential approach to the extraction of shape features
Computer Graphics and Image Processing, 1977