A Comparative Study of Surface and Buried P-Channel 0.10um MOSFETs

1 January 2000

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 544-547
https://doi.org/10.1109/essderc.2000.194835

Abstract

First Page of the Article Author(s) Guegan, G. LPCS/ENSERG, Grenoble, France Deleonibus, S. ; Bertrand, G. ; Souil, D. ; Clerc, R. ; Tedesco, S. ; Heitzmann, M. ; Mur, P.

Keywords

MOSFETS
BORON
DOPING
THRESHOLD VOLTAGE
VOLTAGE CONTROL
ION IMPLANTATION
LITHOGRAPHY
GEOMETRY
LEAKAGE CURRENT
OXIDATION

This publication has 0 references indexed in Scilit: