Design procedure for two-stage CMOS opamp with flexible noise-power balancing scheme
- 15 August 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 52 (8) , 1508-1514
- https://doi.org/10.1109/tcsi.2005.851395
Abstract
This paper presents a basic two-stage CMOS opamp design procedure that provides the circuit designer with a means to strike a balance between two important characteristics in electronic circuit design, namely noise performance and power consumption. It is shown in this paper that, unlike the previously reported design procedures, the proposed design step allows opamp designers to trade between noise performance and power consumption with greater flexibility. In order to verify the viability of the proposed design step, SPICE simulation results of the opamp designed by the proposed procedure, under a variety of temperature and process conditions, are given.Keywords
This publication has 2 references indexed in Scilit:
- Design Procedure for Two-Stage CMOS Transconductance Operational Amplifiers: A TutorialAnalog Integrated Circuits and Signal Processing, 2001
- An optimized compensation strategy for two-stage CMOS op ampsIEEE Transactions on Circuits and Systems I: Regular Papers, 1995