Planar fully ion implanted InP power junction FET's
- 1 July 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 5 (7) , 273-276
- https://doi.org/10.1109/EDL.1984.25915
Abstract
This letter reports on the fabrication and performance of planar all ion-implanted 1.0-µm gate length InP power junction field effect transistors (JFET's). The devices were fabricated utilizing n+ implantation, a AuZn/TiW/Au gate metallization, and an n+ drain ledge. At 4.5 GHz, the 300-µm gate width JFET's exhibited maximum insertion gains of up to 13 dB and scaled output powers as high as 1 W/mm with 3-dB gain.Keywords
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