A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip
- 1 June 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 43 (3) , 1717-1719
- https://doi.org/10.1109/23.507177
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- A delay line loop for frequency synthesis of de-skewed clockPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systemsIEEE Transactions on Nuclear Science, 1995
- A CMOS four-channel*1K time memory LSI with 1-ns/b resolutionIEEE Journal of Solid-State Circuits, 1992