A two-quadrant analog multiplier integrated circuit
- 1 December 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 8 (6) , 434-439
- https://doi.org/10.1109/jssc.1973.1050434
Abstract
A pulse-width-amplitude-modulation approach is used in an integrated-circuit design of a two-quadrant analog multiplier. The circuit described is a single-chip PWAM multiplier of comparable cost to monolithic transconductance multipliers. It requires an external capacitor and a low-pass filter and achieves accuracies better than 0.5 percent without trimming. Temperature stability is typically 0.005 percent per degree Celsius.Keywords
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