Speech preprocessing using analog VLSI

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Abstract
The aim of this project is analog CMOS VLSI implementation of a low-power, real-time front-end processor for speech recognition and for multichannel aids for the deaf. Physiological studies of the mammalian auditory periphery indicate that synchrony coding of speech signals by the temporal pattern of activity in the auditory nerve is noise resistant and performs amplitude compression without distortion over a wide range [M. B. Sachs, H. F. Voigt, and E. D. Young, J. Neurophysiol. 50, 27–45 (1983)]. In a number of studies using digital computation to model the auditory periphery, the properties of synchrony coding of speech signals have been explored [K. L. Payton, J. Acoust. Soc. Am. 83, 145–162 (1988), and articles in J. Phonet. 16, 1 (1988)]. Here VLSI realization of the middle ear, the basilar membrane, and the hair cell and synapse are presented along with design features of the analog VLSI approach. The multichannel outputs correspond to the time-varying firing rates of neurons from discrete places on the cochlear partition.

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