Accurate determination of CMOS capacitance parameters using multilayer structures
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Focuses on the principles and experimental results of accurately measuring very small capacitances on a CMOS integrated circuit. An important feature is that stray capacitance to ground, on either or both nodes of the capacitor, does not alter the measured capacitance value. This allows integration of many relevant design features in small multilayer test structures. The author also presents an implementation of this method in a circuit that accurately extracts the capacitance between stacked layers and fringing capacitance between adjacent signal leads Author(s) De Lange, W. Intergraph Corp., Palo Alto, CA, USAKeywords
This publication has 2 references indexed in Scilit:
- Simple formulas for two- and three-dimensional capacitancesIEEE Transactions on Electron Devices, 1983
- A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuitsIEEE Electron Device Letters, 1982