Selective annealing for the planar processing of HgCdTe devices

Abstract
Hg1−xCdxTe layers grown by organometallic vapor phase epitaxy are p type with carrier concentrations around 4×1016 /cm3 due to group II vacancies. Following a Hg saturated anneal at 220 °C for 25 h, these layers become n type with carrier concentrations around 5×1014/ cm3 . However, the presence of a 0.5–0.8 μm thick CdTe cap inhibits the annealing of the underlying Hg1−xCdxTe layer, since it acts as a barrier for Hg diffusion. By opening windows in this cap, the underlying Hg1−xCdxTe layer can be annealed and converted to n type in a selective manner. P–N junction photodiodes were fabricated using this planar technique. Some of these diodes employed the CdTe cap itself as the surface passivant; in others, the CdTe cap was stripped and anodic sulfide was used as the junction passivant. In both the cases, diodes had R0A values comparable to the best values reported in literature. N-channel enhancement mode metal–insulator semiconductor field effect transistors were also fabricated using anodic sulfide as the surface passivant. Here, the n-type source and drain regions were formed by selectively annealing the as grown p-type Hg1−xCdxTe layer.

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