Planariation technology for Josephson integrated circuits
- 1 August 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 9 (8) , 414-416
- https://doi.org/10.1109/55.762
Abstract
Planarization technology has enabled completion of the multi-level layer structure, which is essential to the achievement of large-scale integration and high-speed operation. A new etch-back planarization technology, using 2000-molecular weight polystyrene, has been developed for Josephson integrated circuits (IC's). This technology has been applied to fabricating the multilevel layer structure in magnetic coupled gates. The results, indicated by their cross-sectional SEM photographs and measured breakdown voltages, show that excellent planarity was achieved in this structure.Keywords
This publication has 1 reference indexed in Scilit:
- Uniform Polymer Coating Technique for an Etch‐Back Planarization Process Using Low Molecular Weight PolymersJournal of the Electrochemical Society, 1988