The Challenges of Hardware Synthesis from C-Like Languages

Preprint

25 October 2007

preprint
Published by arXiv in arXiv

https://doi.org/10.48550/arXiv.0710.4683

Abstract

MANY TECHNIQUES for synthesizing digital hardware from C-like languages have been proposed, but none have emerged as successful as Verilog or VHDL for register-transfer-level design. This paper looks at two of the fundamental challenges: concurrency and timing control.

Keywords

FUNDAMENTAL CHALLENGES
SYNTHESIZING DIGITAL
HARDWARE SYNTHESIS
REGISTER TRANSFER
DIGITAL HARDWARE
TRANSFER LEVEL
LIKE LANGUAGES
LEVEL DESIGN
VHDL

All Related Versions

Version 1, 2007-10-25, ArXiv

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