A new write/erase method for the reduction of the stress-induced leakage current based on the deactivation of step tunneling sites for flash memories
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
This paper describes a new write/erase method to improve the read disturb characteristics by means of drastically reducing the stress-induced leakage current in the tunnel oxide. With the proposed write/erase method, the degradation of the read disturb life time after 10/sup 6/ write/erase cycles can be drastically reduced to 50% in comparison with the conventional bipolarity write/erase method. The features of the proposed write/erase method are as follows: (1) applying an additional pulse to the control gate just after completion of the write/erase operation; (2) the voltage of the additional pulse is higher than that of the control gate in a read operation, and lower than that of the control gate in a write operation; and (3) the polarity of the voltage is the same as that of the control gate voltage in the read operation. This proposed write/erase method is based on the deactivation mechanism of the leakage current, which is discussed in detail in this paper.<>Keywords
This publication has 1 reference indexed in Scilit:
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