Optimized sensing scheme of DRAMs
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (4) , 895-899
- https://doi.org/10.1109/4.34067
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A 90ns 4Mb DRAM in a 300 mil DIPPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A 50-μA standby 1M x 1/256K×4 CMOS DRAM with high-speed sense amplifierIEEE Journal of Solid-State Circuits, 1986
- Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMsIEEE Journal of Solid-State Circuits, 1984
- High sensitivity charge-transfer sense amplifierIEEE Journal of Solid-State Circuits, 1976