A paraller planar generalized Yee algorithm for the analysis of microwave circuit devices

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Abstract
The planar generalized Yee (PGY) algorithm is an extension of the generalized Yee algorithm and the discrete surface integral (DSI) methods, which are based on explicit time‐marching solutions of Maxwell's equations. Specifically, the PGY algorithm exploits the planar symmetries of printed microwave circuit devices, achieving great savings in both CPU time and memory. Since the PGY algorithm is an explicit method, it has a high degree of parallelism. To this end, a highly scalable parallel algorithm based on a spatial decomposition of the general unstructured mesh is presented. Two spatial decompositions are compared, the recursive inertia partitioning (RIP) algorithm and the Greedy algorithm. The Greedy algorithm provides optimal load balance, whereas the RIP algorithm more effectively minimizes shared boundary interface lengths. Through numerical examples, It is demostrated that the Greedy algorithm provides superior speedups. It is also demonstrated that the parallel PGY algorithm is a highly scalable algorithm.