A high speed programmable digital FIR filter

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 15206149,p. 969-971
https://doi.org/10.1109/icassp.1990.116030

Abstract

The implementation of a high-speed, programmable finite impulse response (FIR) filter using coefficients consisting of two power-of-two terms is presented. The area and speed performance figures for this application-specific IC (ASIC) demonstrate the superiority of this architecture for high-speed and high-density implementation. This implementation was developed using a relatively primitive CMOS process. Simple lambda -rule scaling suggests that by using a 1.25- mu m and double-level metal process of the same die size, this architecture will allow the implementation of a filter of approximately 200 taps operating at a 10-MHz sampling rate.<>

Keywords

This publication has 4 references indexed in Scilit:

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