Circuit optimization of the taper isolated dynamic gain RAM cell for VLSI memories
- 1 January 1979
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A one transistor only, ROM like dynamic RAM cell, whose operation depends on the modulation of the threshold of a buried channel device by a hole packet, derived from the channel stop region will be covered. Tapered oxide between the field and gate oxide is used to form a potential barrier for holes.Keywords
This publication has 2 references indexed in Scilit:
- Leakage studies in high-density dynamic MOS memory devicesIEEE Transactions on Electron Devices, 1979
- Stratified charge memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978