Pipelined architecture for fast CMOS buffer RAMs
- 1 June 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 25 (3) , 741-747
- https://doi.org/10.1109/4.102669
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- Pipelined 16k Buffer RAM with 300MHz Operating FrequencyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- A 4ns 16k BiCMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989