A single-chip 16-bit 25 ns realtime video/image signal processor
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 170-171
- https://doi.org/10.1109/isscc.1989.48246
Abstract
A single-chip real-time video/image processor (VISP) has been developed that integrates functions based on a variable seven-stage pipeline arithmetic architecture in a 16-bit fixed-point data format. A three-input adder implemented in complementary CMOS reduced-swing logic, which is twice as fast as conventional CMOS logic, achieving a 25-ns instruction cycle, is shown. Single-VISP processing times are: edge detection (3*3 Laplacian), 14.8 ms; distance calculation, 1.7 ms; temporal filtering (1-tap IR), 5.0 ms; linear quantization, 3.3 ms; and 3/5*3/5 picture reduction (separate 5-tap FIR), 5.9 ms. An example is shown of a two-dimensional discrete cosine transformation which requires 26.3 ms to execute with one VISP when 256*256 pixel processing at a 25-ns instruction cycle is employed.<>Keywords
This publication has 1 reference indexed in Scilit:
- A realtime microprogrammable video signal LSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987