A large scale FPGA with 10 K core cells with CMOS 0.8 mu m 3-layered metal process

9 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 6.4/1-6.4/4
https://doi.org/10.1109/cicc.1991.164125

Abstract

A large-scale FPGA (field-programmable gate array) that contains 10 K core cells is described. The core cell, a programmable logic module, consists of a two-input NAND gate, a latch circuit, and bus drivers. The function of one core cell is estimated to be equivalent to four NAND gates. As a result, the FPGA integrates a total of 40 K gates. Configuration data are stored in SRAMs on the device. A booster circuit on the chip supplies higher voltage to reduce on-resistance of the switch elements to ensure high-speed operation. This FPGA has two programming modes, the BFR (boot from ROM) mode, in which the FPGA accesses outer nonvolatile memory devices, and the CPU mode, which is controlled by a CPU as a peripheral device. A probe system is implemented on the device to read the output signal of each core cell to realize swift debugging of configured circuits.<>

Keywords

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