A scalable systolic array architecture for 2D discrete wavelet transforms

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 303-322
https://doi.org/10.1109/vlsisp.1995.527501

Abstract

A systematic synthesis approach has been developed for scalable systolic array architecture for a 2D discrete wavelet transform (DWT) based on the data dependence analysis and linear index space transformation. The proposed architecture has regular topology, local routing, simple controller and high throughput rate. It can be easily extended to different parameters of various levels, macroblocks and filters. The derived architecture has been prototyped using Cadence Edge Framework.

Keywords

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